The present inventions are related to systems and methods for alleviating analog to digital converter mismatches.
Analog to digital converters are a staple in mixed signal semiconductor designs as they allow for operation on signals in both the digital and analog domains. In some cases, a mixed signal semiconductor device may employ a large number of analog to digital converters allowing the implementation to accept and process a large number of inputs. When multiple analog to digital converters are utilized, such as in a read channel device, there may be some mismatch between one or more of the analog to digital converters. The mismatch is typically in the form of, among other things, different gains, different offsets, and/or different comparator threshold voltages. These mismatches pose a serious problem to adaptive digital loops that retain a preceding completion point in memory to be used as a succeeding initialization point. Thus, for example, this may be a problem where the completion point of a preceding sector is maintained as an initialization point for a succeeding sector in a read channel device as the previous sector may have relied on a different analog to digital converter than that utilized by the succeeding sector. Such a scenario may result in unacceptable servo burst demodulation problems and/or into undesirable timing and gain control effects.
To address the aforementioned limitations, some designs have utilized a single analog to digital converter tasked with performing a wide array of operations. Turning to FIG. 1, a prior art system 100 relying on a single, complex analog to digital converter 110 covering a spectrum of operations is shown. Analog to digital converter 110 receives an analog input 105 and provides a digital representation of analog input 105 to a gain loop 120. Gain loop 120 performs is particular function and provides a result to a shadow register 130. Shadow register 130 stores the output of gain loop 120 whenever indicated by the completion of one of a number of events as denoted by the output of an OR gate 140. Shrinking feature sizes in CMOS technologies pose severe limitations to system 100 where varied temperature, voltage and other factors can render the design of analog to digital comparator 110 complex and power inefficient. To avoid the limitations of system 100, some designs have used multiple analog to digital comparators that may be relatively simple designs, but that include inherent mismatches. In addition, a dedicated microprocessor is used to implement a sophisticated calibration scheme to alleviate the effects of the inherent mismatches. Usually, the calibration procedure is done before the device resumes normal operation. It should be noted that even after extensive calibration, all mismatches will not necessarily be eliminated and may continue to adversely effect operation.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for operating in relation to analog to digital converters.